Atmel ATF1504AS(L) CPLD Development Board - Part 7 - Using a Clock ( clk )

Buttons and LEDs are fine but it really doesn't come close to interfacing with real hardware.  So now to take the human element out of the equation and time to use a clock.

For this experiment I am using a 1 Mhz crystal oscillator.  It doesn't sound very fast but the untrained human eye can only really see somewhere less than 100Hz (see various debates on this on the internet).

This isn't a step by step, but I've given you big hints on how to avoid the big issues.

Happy learning!

The BOM

For this experiment I will be using the following items:

• 1 x CPLD Dev board
• 1 x LED array ( as seen previously, or you can just use 1 LED and a resistor )
• 2 x 4017 decade counters
• 1 x 1 Mhz crystal oscillator, any 5 volt, 1Mhz  4pin crystal oscillator will do.
• 1 x 01.uF capacitor
• Lots of Jumper wires
• LA2016 Logic Analyzer ( or any logic analyzer that can handle 5v )  (optional bonus content)
  

 

Failing and learning ( get a Logic Analyzer )

The one thing I learnt early on when constructing this experiment was that I simply could not get the clock division down to a low enough level to see the result.  What I really needed was a Logic Analyzer so I could actually see what was going on.  I went over and over the code trying to work out what was wrong with it and . . . there was nothing wrong.  I just didn't have the right instruments to tell me I was ok.

If you are going to continue your journey with CPLD's and FPGA's you are going to need one.  Go buy it now or you will just be frustrated.

Failing and learning part 2 (tie down all of the control input pins on the 4017)

 

The second issue I had was just failing to ground the reset and clock enable pins on the 4017.  Don't let control inputs float.  Either connect them to ground or to power.  I only realized at the end that I had not tied the reset pin to ground.  So frustrating.

 

Failing and learning part 3 (assign ALL pins on the CPLD)

I got mighty confused with the clocking because of the way the compiler works.  If you don't assign all of the outputs the compiler will assign random outputs on the internal buses that are not assigned to unassigned pins.  If you don't want to see output then assign them all to 0.

 

Example code

 

I originally wrote the code in Verilog, but as I didn't have a Logic Analyzer I failed and looked around for some example code.  Eventually I found Bil Herds example program on Hackaday and modified it for my own use.

 

The source is just a plain rip-off of Bil's project with a few modifications with the help of old school wisdom from my cousin.

Here are the pin assignments.

 

Why are you using 4017 decade counters?

 

This is pretty simple really.  When I first started this project I made some really rookie errors and couldn't get the clock less than about 122Hz with a little advice I managed to get it to work properly and no longer need them.

 

However, it is fun to used them and we get to learn a little more about how to interface with the CPLD.

Wiring up the board and Logic Analyzer output

 

Looking at the Analyzer you can see a number of signals.

1. This signal is the clock itself at 1MHz.
2. This is the output of the first CPLD counter at 3.90KHz
   
3. This is the output of the second CPLD counter at 49.90Hz
   
4. This is the output of the third CPLD counter at around 0.06Hz +/- a bit
   

 

Plugging the second CPLD output into the 4017's makes the LED flash a around once every 3 seconds.

And here is the finished product.