Atmel ATF1504AS(L) CPLD Development Board - Part 8 - Replacing Logic 74HC00

Time to experiment with replacing Logic chips.  This time I am going to replace a 74HC00 on a Z80-MBC2 board.

It's important to review not only the data sheet for the 74HC00, but also the Z80-MBC2 to ensure that it is appropriate.  For this experiment everything is running at 5Volts so it is safe to proceed.

You don't need a Z80-MBC you can just connect A and B to the VCC and GND lines in combinations and the Y lines to some LEDs.

However I wanted to see if it would work in a REAL system.

You can go to Hack a Day to learn more about the Z80-MBC.

 

74HC00 Datasheet

Let's first review the Datasheet, specifically we need to know how the 74HC00 operates and the pin out.  In this case it is very easy, there are four NAND gates in the DIP.

 

It should be strongly noted that we are implementing LOGIC only with the CPLD.  Some Logic chips have built in electrical characteristics that can not be replicated by the CPLD

 

Replicating the 74HC00 in Verilog

Now it's time to replicate the 74HC00 in Verilog.

As you can see on the image above there are Four NAND gates.

 

To save time having to type out each gate individually you can create an array of pins, the following declares 4 pins ( 0,1,2 and 3 ).

 

     input [3:0]  pinA

 

which is much better than this

 

    input pinA0    

    input pinA1

    input pinA3    

    input pinA4

 

Each gate has Two Inputs ( A and B ) and One Output ( Y ).

The Two inputs A and B are AND'ed togther and then the result is NOT'ed ( reversed ).

 

    Y = NOT ( A AND B )

 

In Verilog this is as follows where x is the pin number in the array.

 

    assign y[x] = ! ( a[x] & b[x] ) 

 

Let use also allocate the pins in a logical way in the Pin Planner.

Hooking it all up

Finally let's hook it up to the Z80-MBC2.  It is a bit tight for space so take your time with the wires.  I am using the Z80 to power the CPLD via pins 7 GND and 14 VCC.

Without the 74HC00 installed the computer stops at the line" IOS: Z80 is running from now".

It lives, the user prompt is ready and waiting for action.

Atmel ATF1504AS(L) CPLD Development Board - Part 7 - Using a Clock ( clk )

Buttons and LEDs are fine but it really doesn't come close to interfacing with real hardware.  So now to take the human element out of the equation and time to use a clock.

For this experiment I am using a 1 Mhz crystal oscillator.  It doesn't sound very fast but the untrained human eye can only really see somewhere less than 100Hz (see various debates on this on the internet).

This isn't a step by step, but I've given you big hints on how to avoid the big issues.

Happy learning!

The BOM

For this experiment I will be using the following items:

• 1 x CPLD Dev board
• 1 x LED array ( as seen previously, or you can just use 1 LED and a resistor )
• 2 x 4017 decade counters
• 1 x 1 Mhz crystal oscillator, any 5 volt, 1Mhz  4pin crystal oscillator will do.
• 1 x 01.uF capacitor
• Lots of Jumper wires
• LA2016 Logic Analyzer ( or any logic analyzer that can handle 5v )  (optional bonus content)
  

 

Failing and learning ( get a Logic Analyzer )

The one thing I learnt early on when constructing this experiment was that I simply could not get the clock division down to a low enough level to see the result.  What I really needed was a Logic Analyzer so I could actually see what was going on.  I went over and over the code trying to work out what was wrong with it and . . . there was nothing wrong.  I just didn't have the right instruments to tell me I was ok.

If you are going to continue your journey with CPLD's and FPGA's you are going to need one.  Go buy it now or you will just be frustrated.

Failing and learning part 2 (tie down all of the control input pins on the 4017)

 

The second issue I had was just failing to ground the reset and clock enable pins on the 4017.  Don't let control inputs float.  Either connect them to ground or to power.  I only realized at the end that I had not tied the reset pin to ground.  So frustrating.

 

Failing and learning part 3 (assign ALL pins on the CPLD)

I got mighty confused with the clocking because of the way the compiler works.  If you don't assign all of the outputs the compiler will assign random outputs on the internal buses that are not assigned to unassigned pins.  If you don't want to see output then assign them all to 0.

 

Example code

 

I originally wrote the code in Verilog, but as I didn't have a Logic Analyzer I failed and looked around for some example code.  Eventually I found Bil Herds example program on Hackaday and modified it for my own use.

 

The source is just a plain rip-off of Bil's project with a few modifications with the help of old school wisdom from my cousin.

Here are the pin assignments.

 

Why are you using 4017 decade counters?

 

This is pretty simple really.  When I first started this project I made some really rookie errors and couldn't get the clock less than about 122Hz with a little advice I managed to get it to work properly and no longer need them.

 

However, it is fun to used them and we get to learn a little more about how to interface with the CPLD.

Wiring up the board and Logic Analyzer output

 

Looking at the Analyzer you can see a number of signals.

1. This signal is the clock itself at 1MHz.
2. This is the output of the first CPLD counter at 3.90KHz
   
3. This is the output of the second CPLD counter at 49.90Hz
   
4. This is the output of the third CPLD counter at around 0.06Hz +/- a bit
   

 

Plugging the second CPLD output into the 4017's makes the LED flash a around once every 3 seconds.

And here is the finished product.